A C++ implementation of an 8-bit CHIP-8 virtual machine interpreter, designed to emulate the core instruction set and hardware architecture of the original system. The project implements the complete fetch-decode-execute cycle, including 4KB of memory, 16 general-purpose registers, stack-based control flow, and all 35 core CHIP-8 opcodes.

The interpreter also integrates SDL2 to emulate the CHIP-8's 64×32 monochrome display and keyboard input. Timing and sound functionality are handled using std::chrono, with the delay and sound timers synchronised around the CHIP-8's 60Hz timer rate.

To validate the implementation, Catch2 unit tests were used to test opcode execution and verify that individual instructions produced the expected changes to registers, memory, and machine state.

• Technologies UsedC++, SDL2, Catch2